Fault Injection

Discussion on the justification for SJTAG in each of the identified Use Cases: Alternatives, cost benefits and penalties
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Ian McIntosh
SJTAG Chair
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Fault Injection

Post by Ian McIntosh »

Meeting minutes reference:
http://www.sjtag.org/minutes/minutes071217.html


JTAG presents the opportunity to support hardware and software design verification activities, offering a non-intrusive means of setting pin/net states to simulate fault conditions. At a system level, this means that faults may be injected without disturbing the system configuration, e.g. introducing extender cards or attaching temporary "wire links".

In turn, this increases the scope for more comprehensive design validation under environmental test conditions (thermal, vibration, EMC), an area which is traditionally considered difficult.

Edit: Added the following to summarise meeting discussions:

One problem with JTAG is that putting a device into EXTEST takes all of its pins out of functional mode - this may limit usability, although there are some methods that have been used with FPGAs to allow selected pins to be used for fault injection.

Also, JTAG does not readily allow for simulation of AC/transient faults; only DC/"stuck at" faults, although IEEE 1149.6 may open up some possibilities here.

However, JTAG does offer the opportunity to re-test using new or updated fault models without the need to modify the target system.
Last edited by Ian McIntosh on Thu Jun 11, 2009 6:43 am, edited 1 time in total.
Reason: Added link to minutes
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Yingwu Li
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Location: Huawei, Shenzhen, China

Not all, need only one

Post by Yingwu Li »

After putting a device into EXTEST, that takes all of its pins out of functional mode. But many requirements is hoping that takes only one of its pins out of functional mode in the fault simulation. However we all know that is impossible. So the usablity is very limit. :(