Drivers for Hardware Architecture - Brainstorm

Hardware Architectures Document
Please debate the content of Volume 3 here!
User avatar
Ian McIntosh
SJTAG Chair
Posts: 504
Joined: Mon Nov 05, 2007 11:49 pm
Location: Leonardo, UK

Drivers for Hardware Architecture - Brainstorm

Post by Ian McIntosh »

The bullet points we raised at the November 23 meeting:
  • Need to deal with multiple assemblies in a system
  • When externally controlled, generally a single TAP is desired
    • Multiple TAPs, e.g. for concurrency, like Intellitech cJTAG, shouldn't be discounted
  • Means to isolate assembly under test from other signals on the backplane
  • Co-existence of embedded control with option for external control
  • Signals going off-board must not be floating (DFT rules)
  • Fan-out may be large, especially across large backplanes
  • Individual control of tests in a FRU
  • Signal integrity of 5-wire TAP when taken external to a system
  • Uniformity of interface - don't mix multi-drop and star
  • Means to address assemblies:
    • "Slot code"
    • Hardwired by board type
    • Mixture of the two
Please reply with additions to the above, or with comments and observations.
Ian McIntosh
Testability Lead
Leonardo UK
User avatar
Ian McIntosh
SJTAG Chair
Posts: 504
Joined: Mon Nov 05, 2007 11:49 pm
Location: Leonardo, UK

Re: Drivers for Hardware Architecture - Brainstorm

Post by Ian McIntosh »

Additional point raised at the November 30th meeting:
  • Security
    • Protect against unauthorised retrieval of firmware, software or other device register contents
    • Protect against substitution of unauthorised firmware or software or other device register contents
    • Permit access for board test
    • Restrict retrieval of circuit design information
There is a thread dedicated to this topic: viewtopic.php?f=29&t=111
Ian McIntosh
Testability Lead
Leonardo UK
User avatar
Bradford Van Treuren
SJTAG Chair Emeritus
Posts: 152
Joined: Fri Nov 16, 2007 2:06 pm
Location: VT Enterprises Consulting Services, USA

Re: Drivers for Hardware Architecture - Brainstorm

Post by Bradford Van Treuren »

To try to stimulate more discussion on the subject of management requirements SJTAG needs to support, I offer the following diagram and description to help gain more insight into the problem space to assist our group.
SM_AM.jpg
System Manager:
  • Tracks and records the configuration and state of the system
  • Regulates the operational state of each assembly in the system
  • Communicates configuration and state information to the outside world through an external interface
  • Applies operations/functions to the system as requested by the external inteface
Assembly Manger:
  • Tracks and records the configuration and state of any sub-assemblies that make up this assembly
  • Regulates the operational state of each sub-assembly that makes up this assembly
  • Applies operations/functions to the assembly as requested by the System/Parent Assembly Manager
For POST or self initiated testing, the assembly manager would post its state information in a publically accessible memory resources (e.g., dual ported RAM, FLASH file system) where the system manager could extract the inforation in a pull control model or the assembly manager could asynchronously send a message to the system manager with any configuration or state change in a push control model.

Ideally, the information is maintained by the system manager on a softare bulletin board/data base resource.
You do not have the required permissions to view the files attached to this post.
Bradford Van Treuren
Distinguished Member of Technical Staff
VT Enterprises Consulting Services
User avatar
Ian McIntosh
SJTAG Chair
Posts: 504
Joined: Mon Nov 05, 2007 11:49 pm
Location: Leonardo, UK

Re: Drivers for Hardware Architecture - Brainstorm

Post by Ian McIntosh »

The slides I used during today's meeting, work from the opposite end that Brad's do. I was trying work things from a viewpoint of how a system typically appears and what the problems are that are presented for JTAG, since that's fundamentally what SJTAG is trying to solve.

http://files.sjtag.org/IanMc/Back2Basics.pdf

What I'd hoped to do was build up layers or overlays on the basic physical architecture that showed how the management and routing entities we'd identified could be placed, but I wasn't finding it easy :?
Ian McIntosh
Testability Lead
Leonardo UK