PURPOSE: The purpose of this standard is to provide a means to seamlessly integrate component access topologies (that follow a Capture, Shift, Update Cycle), interface constraints, and other dependencies at the board and system level with a uniform description that focuses on topology and behavior (as opposed to physical structure). By modeling this topology at the board and system level, a common set of interfaces may be used by higher level tools defined to coordinate these access topologies (communication interfaces) providing and provide a means of routing data sets to particular destination registers in the correct time order.
We also added two bullet points for Seamless Access and one for Problem Domain. The new set of brainstorm items is:
- Seamless Access
- system, board, device meld into a uniform description (Abstraction of “Assembly”)
- Behavioral aspects than structural
- treat the interfaces (access links, data links) as "black boxes“
- Standardize on the right-hand side following the CSU protocol.
- Schedule, Order, Application of vectors
- Provide a means for higher level tools to make use of
- Problem Domain (what we are trying to do)
- Inadequacy of existing standards
- Aggregation of circuit boards (w/ varying protocols e.g., 1149.x, 1687, I2C, USB, SPI)
- Trying to create a software abstraction to the existing hardware standards