TAPs, boundaries and systems

Discuss the generic proposals for SJTAG
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Michele
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TAPs, boundaries and systems

Post by Michele » Thu Apr 16, 2015 12:01 pm

With this subject that seems taken from the Hitchicker's Guide to the Galaxy, I will and explain some doubts and thoughts that I have been having.

We spent many meeting speaking about BS linkers, and how SJTAG should support and manage them. This is quite normal if we look at our reference system: each element is an independent chip, so it is just logical to assume that their interface will be a TAP.
But if we take a deeper look inside the chips, there usually are one or more TAPs inside them too. 1687 call them "embedded TAPs", but the "e" comes only for their physical location. Functionally, it is just the same as if they were on the outside. Similarly, I have seen at ITC14 some slides from the 1838 for 3D-test standard where they are proposing to have a TAP in each die
1838.jpg
...so, what about them? Where do we stand?

From what I see, all these TAPs should be seen as the entry point for SJTAG: just like we should support linkers like the BSCN2 or ASP, we should at least go as far as any TAP, supposing the "system" starts from there. This would give SJTAG a great power as it would then be able to really put together all subsystems, but it also widens up the problem significantly because we then should be able to support "any" combination of TAPs and "glue logic".

Any thoughts?

Michele

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Ian McIntosh
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Re: TAPs, boundaries and systems

Post by Ian McIntosh » Tue May 12, 2015 7:46 am

To be honest, I haven't really been following what's happening in P1838 - it's likely to be some time before I see any of those stacked die parts on boards in our systems and I'll worry about them once they appear on my horizon and even 1687 is probably some way off for us.

However, looking at the P1838 example given, from the way it is drawn it looks like the TAP Controllers could be arranged as if they were in a multidrop configuration but I suspect the real intent was for the three dice to be arranged as a chain. Thus, there is no additional addressing protocol, and it is simply down to the position of a die in the chain. That being the case, the stacked die part is essentially a sub-system or sub-assembly, much like a mezzanine would be, and would be handled by SJTAG in the same way. The difference might be that while you would tend to put a mezzanine or daughter-board in it's own chain or downstream of a bypass element (so that the chain isn't broken by an absent plug-in), the 3D part may well be inserted into the middle of a chain.

In any case you'd need to know the order of the dice and have the BSDLs, etc., for each. I'm assuming that each die will have its own BSDL rather some kind of rolled-up super-BSDL, especially if one of the die is configurable and might need a post-config BSDL created.
Ian McIntosh
Testability Lead
Leonardo MW Ltd.

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