bidirectional TAP signals

[Tim Pender]

Dot 1 uses unidirectional TAP signals while emerging standards (dot7) are changing the TAP to use 2 or 4 wires and allowing bidirectional data flow.
How will this be accomplished on a board level where buffers are being used, even if bidirectional buffers like a 245 are being used, a discrete line will be needed to control the direction, what controls the direction of the buffer? This methodology would be accomplished much easier with open drain configuration but throughput would suffer because rise times are slow.

[Ian McIntosh]

I can certainly understand the drive to reduce the TAP pincount at a device level, but I wonder how strong the desire to save a couple of pins at the board level is? I suspect it'll be a "chicken and egg" question - you won't get (much) device availability until there's a market, and no market until there's availability. In the face of an 1149.1 that works now, I think it might be a hard fight to get adoption of 1149.7, because of the kind of question Tim asks.

Ethernet manages the kind of "multiple access" that 1149.7 needs, and at speed, but at the expense of being undeterministic. But there must also be a throughput penalty in not being able to clock vectors in and out simultaneously, assuming you can recover to 1149.1 type clock rates.