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Generic Gateway Features

Hardware Architectures Document
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Ian McIntosh
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Generic Gateway Features

Postby Ian McIntosh » Mon Jun 28, 2010 8:27 pm

Post suggestions (and any pertinent explanations) of features that ought to be considered key for an SJTAG compliant gateway device. For now, concentrate on the gateway aspect only, as we'll tackle linking, etc. later.

I'll try to maintain a summary list here:
  • Adressability
  • Dynamic path selection
  • Digital (GPIO) signal pass through
  • Unique addressing for each physical hierarchical path
  • Extensible protocol to support various numbers of secondary paths
  • Each level of the hierarchy is addressable from the top level
  • Scan chain topology should be identical from an external or embedded TAP Interface allowing external tools to be used to prove-in tests that can then be directly reused embedded environment (once only prove-in)
  • Scan chain topology should be identical whether testing from a local on-board or external TAP Interface and a multi-drop TAP Interface (test reuse)
Last edited by Ian McIntosh on Tue Jul 13, 2010 7:38 am, edited 1 time in total.
Reason: Amended 7th bullet
Ian McIntosh
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Peter.Horwood
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Re: Generic Gateway Features

Postby Peter.Horwood » Mon Jun 28, 2010 9:22 pm

A SJTAG gateway device should support at least these 2 features of : Addressability, dynamic chain selection,

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Heiko Ehrenberg
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Re: Generic Gateway Features

Postby Heiko Ehrenberg » Tue Jun 29, 2010 3:02 am

Providing a means to pass through digital signals (GPIO) in addition of TAP signals is beneficial.
- Heiko

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Bradford Van Treuren
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Re: Generic Gateway Features

Postby Bradford Van Treuren » Sun Jul 11, 2010 11:27 pm

Here is a list I thought of:
  • Unique addressing for each physical hierarchical path
  • Extensible protocol to support various numbers of secondary paths
  • Each level of the hierarchy is addressable from the top level
  • Whether testing from an external or embedded TAP Interface, the topology of the scan chain should be identical allowing test develoment with external tools to be reused and already proven-in for the embedded environment.
  • Ideally, the topology of the scan chain should be identical whether testing from a local on-board or external TAP Interface and a multi-drop TAP Interface to allow for a common test suite for all interface domains yielding to true test reuse and portability.
Bradford Van Treuren
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Tim Pender
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Re: Generic Gateway Features

Postby Tim Pender » Mon Sep 27, 2010 6:26 pm

Additional Features
Chain Tap State readback register
I think it would be a useful feature for the host to query a gateway register to find out what the current tap state of a chain. What I envison is a tap monitor with 4 bits per chain.
Often times Tooling software will hardcode a test-logic-reset to get the system in a known state before applying vectors, a more versitile method would be to query registers in a SJTAG Gateway. Applying hardcoded resets in the interconnect test may undo preconditioning. Some extra register bits may be used to for embedded systems utilizing I2C or like protocols to manage/synchronize chain selections.

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Heiko Ehrenberg
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analyzing the Gateway environment ...

Postby Heiko Ehrenberg » Mon Dec 06, 2010 10:01 pm

In our Dec 7 2010 conference call we tried to formulate a definition for Gateway devices, but then took a step back and decided first to analyze the environmental factors for Gateway devices. The following is a list of thoughts in regards to Gateway environments:

  • that multiple scan chains that need to coexist;
  • multiple scan chains may have to work in concert with each other;
  • may need to manage the bridging of non-JTAG signals (although: which direction and how many)
  • need to specify a standard voltage level on the primary side
  • Gateway needs to enable or disable access to individual scan chains
  • access commands must be coordinated with scan operations on the TAP
  • the primary side of a Gateway device may be connected to a bussed environment (multi-drop) or in a star configuration
- Heiko


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