Meeting Minutes reference:
My perception of BIST is that it addresses functional test rather than structural test, so while an interconnect test may establish whether or not the physical assembly of the UUT is correct, BIST will help to determine if the logical function of a device (or group of devices) is correct.
BIST, at a board level, may exploit internal BIST features of a device, and similarly BIST, at a system level, may exploit the BIST features of the boards in that system. So, do we infer that boards/FRUs should incorporate a BIST controller that reports to the system level (Device BIST is often only executable by JTAG indirectly (if at all) and the same applies to the collection of test results)?
During BIST, the board/FRU boundaries must remain in a "safe" state to ensure that false stimuli are not propagated through the remainder of the system. Does this imply that board level BIST is compromised within a system?
It may well be part of the functional requirement of the system to provide a BIST capability. It is possible that the designer might feel that using JTAG to meet this requirement adds unnecessary complication, so what arguments can we present to promote a JTAG based BIST?
Discussion on the justification for SJTAG in each of the identified Use Cases: Alternatives, cost benefits and penalties
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