Study Group title; here are some proposals; please vote on those or propose another:
- System Test Access (STA)
- System TEst Access Management (STEAM)
- Test Engineering and Maintenance Access (TEMA)
- System Test Engineering Access and Maintenance (STEAM)
Please provide your input both on the title and the text as soon as possible.This is a call for participation in the [title] Study Group (previously referred to as 'SJTAG'). Those interested in joining the Study Group or being kept informed of its activities should notify their interest by email to email@example.com or via the Contact Page.
IEEE 1687 (a.k.a. iJTAG) and IEEE 1149.1-2013 (often referred to as JTAG) provide methods for describing instrument interfaces on a per component basis, but do not provide the contextual prerequisites for the dependence on each instrument configuration and/or aggregation of multiple instruments for the overall board and/or system maintenance operations. Further, many components only support non-JTAG interfaces (e.g., I2C or SPI) to their instrumentation registers.
A new supervisory standard is required to define the coordination and dependencies of instruments as well as configuration, management, and application of vector based testing at the board and system levels, utilizing the pin level access provided by other standards.
The goal of this study group is to explore the feasibility and to develop a project authorization request (PAR), including the scope and purpose, for an IEEE standard that defines methods to allow, in conjunction with existing methods, for the coordination and control of device, board, and sub-system test interfaces to extend access to the system level, by leveraging existing test interface standards (by defining a description to better manage how they are used in the system).
Among the use cases to be considered by such a standard are structural and functional test, configuration / tuning / instrumentation, software debug, built-in self test, fault injection, programming / updates, root cause analysis, failure mode analysis, power-on self test, environmental stress test, and device versioning.