Major Takeway Points

Discussion and feedback on the SJTAG Initiative Group weekly meetings.
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Ian McIntosh
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Major Takeway Points

Post by Ian McIntosh » Tue Jan 11, 2011 2:48 pm

Use this thread to list the main point(s) of interest from the weekly meetings. This could be some significant insight, learning outcome or key question that was raised.

Include a pointer to which meetings minutes these are taken from (you can simply paste in the URL of the minutes page).

Block "owners":
  • Q4 2007 - Heiko
  • Q1 2008 - Ian
  • Q2 2008 - Patrick
  • Q3 2008 - Eric
  • Q4 2008 - Adam
  • Q1 2009 - Peter
  • Q2 2009 - Brian
  • Q3 2009 - Brad
  • Q4 2009 - Tim
  • Q1 2010 - Carl
  • Q2 2010 -
  • Q3 2010 -
  • Q4 2010 -
Last edited by Ian McIntosh on Mon Jan 31, 2011 5:37 pm, edited 2 times in total.
Reason: Added Carl
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Re: Major Takeway Points

Post by Ian McIntosh » Sat Jan 22, 2011 9:57 pm

Q1 2008
Minutes of Weekly Meeting, 2008-01-07 http://www.sjtag.org/minutes/minutes080107.html
Discussion of Structural Test use case
  • Constraints on board edge signals are critical for system level test.
  • Control of clocks: Don't want to be dependant on system clocks, but may be necessary for testing memories.
  • Memory tests must take care not to destroy fault or other essential data.
Minutes of Weekly Meeting, 2008-01-14 http://www.sjtag.org/minutes/minutes080114.html
Discussion of Structural Test use case
  • We need a methodology to lower test generation effort while providing a means to protect IP
  • JTAG can allow an OEM vendor to provide a detailed test without exposing IP in the way that a functional test might
Minutes of Weekly Meeting, 2008-01-23 http://www.sjtag.org/minutes/minutes080123.html
Discussion of Structural Test use case
  • Structural test results in embedded execution:
    • Storage space for results may be limited
    • Should results be transmitted in a standard format?
    • Is a binary or ASCII format preferred?
  • The level of diagnostic detail required may depend on the test context - where performed, what assembly level
Minutes of Weekly Meeting, 2008-01-28 http://www.sjtag.org/minutes/minutes080128.html
Discussion of POST use case
  • POST executuion time is often constrained by a customer requirement
  • OEM implementations may compromise system POST time budgets
  • Need method to recover after POST - e.g. to reboot and skip POST requires some semi-persistent state variable
Minutes of Weekly Meeting, 2008-02-04 http://www.sjtag.org/minutes/minutes080204.html
Discussion of POST use case
  • Test data should be exported from tools using an existing ASCII format: System integrator/User can then convert to most suitable form for their application
  • For embedded cases, a question over whether a diagnostic is required at run time or data stored for off-line analysis
Minutes of Weekly Meeting, 2008-02-11 http://www.sjtag.org/minutes/minutes080211.html
Discussion of POST use case
  • Types of test run during POST are application dependant - can't make assumptions
  • POST should be autonomous at the FRU level
  • POST need not consider board-to-board test
Minutes of Weekly Meeting, 2008-02-20 http://www.sjtag.org/minutes/minutes080220.html
Discussion of POST use case
  • "A use case is orthogonal to a test."
  • "Use cases help break down the types of tests that are appropriate at each state of a product life cycle."
  • POST is generally intrusive
  • May need to account for system states
    • On-line or active
    • Off
    • Off-line
    • Standby
  • Running POST on a hot-swapped FRU will disrupt system operation
Minutes of Weekly Meeting, 2008-02-25 http://www.sjtag.org/minutes/minutes080225.html
Discussion of Programming and Updates use case
  • Brad listed several relevant papers from BTW02 and BTW03
  • Need to ensure a board does not become unrecoverable if an update goes wrong
  • Performing updates via network connection can be a major cost saver
  • BScan may be a recovery option, complementing more efficient FLASH loading methods
Minutes of Weekly Meeting, 2008-03-03 http://www.sjtag.org/minutes/minutes080303.html
Discussion of Programming and Updates use case
  • Routine FPGA configuration via JTAG may lead to excessive board startup times
  • Depends on application whether it is better to swap a FRU or to update in the field
Minutes of Weekly Meeting, 2008-03-10 http://www.sjtag.org/minutes/minutes080310.html
Discussion of Programming and Updates use case
  • Different categories of update:
    • Predictable - e.g. for customer requirements - update of application software - programmed via mission bus
    • Unpredictable - e.g. maintenance, bug fixes, enhancements - update of CPLD or FPGA code - programmed via various methods
  • NAND Flash present different challenges to NOR Flash
  • Loading Boot Code via JTAG, then using Mission Bus for all other loading is a common practice
Minutes of Weekly Meeting, 2008-03-19 http://www.sjtag.org/minutes/minutes080319.html
Discussion of Environmental Stress Testing use case
  • EST can be a motivation for embedding BScan
    • Simplified cabling compared to functional testing
    • Short test times suits being used during thermal ramps
  • Needs some form of external, overall control
  • Large volumes of test data could be produced
    • Where do you store it?
    • How (and where) do you analyse it?
  • BScan may stress the board more than mission mode operation
Minutes of Weekly Meeting, 2008-03-31 http://www.sjtag.org/minutes/minutes080331.html
Discussion of value proposition for Programming/Updates
  • TCK speeds are a problem for programming large FPGA/Flash devices
  • FPGAs and CPLDs will lose functional mode while device programming is taking place
  • STAPL or SVF may be adequate languages for programming
Last edited by Ian McIntosh on Mon Jan 31, 2011 8:47 am, edited 3 times in total.
Reason: Reformatted and added more data
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Re: Major Takeway Points

Post by Heiko Ehrenberg » Mon Jan 24, 2011 1:00 am

SJTAG meeting minutes - key takeaways - Q4/2007
===========================================

2007-10-05
~~~~~~~~~~
- discussion was focused on ATCA and microATCA
- we need to support 3 views for JTAG on each board:
  • Edge access from the backplane,
  • local embedded JTAG controller, and
  • External Tester interface
- at least in ATCA, interoperability between vendor blades [boards] is going to be key
- a system needs to support a uniform protocol at the backplane so boards may be purchased from multiple vendors and conform to the same testing interface for the system to be able to work
- key considerations for SJTAG include:
  • signal integrity;
  • performance;
  • protocol isolation / multi-vendor interoperability;
  • signal voltage levels (microTCA: 3.3V; Patrick: we may need lower voltages, I/O level flexibility);
  • real estate available for JSM implementation and signal routing;
http://www.sjtag.org/minutes/minutes071005.html

2007-10-12
~~~~~~~~~~
- more details on ATCA

2007-10-19
~~~~~~~~~~
- need to emphasize that carrier blades are really subsystem, requiring their local JTAG infrastructure to be immune to changes in the AMC blade configuration
- need to be able to hot-swap blades that are "off-line", needs to be managed by system software, prohibit blades to be removed (put in hot-swap mode) that are currently being tested;
http://www.sjtag.org/minutes/minutes071019.html

2007-10-29
~~~~~~~~~~
- no key takeaway

2007-11-05
~~~~~~~~~~
- discussion of the role SJTAG should play in a system

2007-11-12
~~~~~~~~~~
- Discussion on retaining the fault diagnostics in the system
- Some systems will test at PCB level with one vendor and at system level diagnostic by another. Info must be transferable between vendors.
http://www.sjtag.org/minutes/minutes071112.html

2007-11-19
~~~~~~~~~~
- continuing discussion on retaining the fault diagnostics in the system
- we need to show the cost advantages for using system level JTAG;
http://www.sjtag.org/minutes/minutes071119.html

2007-11-26
~~~~~~~~~~
- Discussion of concerns over how to implement 4 pin JTAG interface if hosted from ATCA HUB boards which must also be tested by external tester.
- we need a connector (interface) for the external tester; interface must be on HUB board to facilitate connection and arbitration to the system; real problem is the arbitration of which ATCA HUB is going to be master;
- Embedded Boundary Scan controller must not be active on backplane by default, to allow external tester to drive the chain (external tester could then be the primary access point by default);
http://www.sjtag.org/minutes/minutes071126.html

2007-12-03
~~~~~~~~~~
- discussion on "What are we trying to achieve?"
- started discussion on use cases;

2007-12-10
~~~~~~~~~~
- discussion of operating procedures for group;
- decision to use forum for SJTAG use case discussions

2007-12-17
~~~~~~~~~~
- SJTAG Value Proposition - Fault Injection:
  • physical modifications (wires, extender cards, ...) may be needed to insert faults, but this may not allow simulation of real faults, also, it changes the environment (systems cannot be sealed, temperature changes, etc.);
  • extender cards and similar physical modifications also degrade performance of the system by changing the characteristics of the nets;
  • problem with JTAG is that putting a device into EXTEST takes all of its pins out of functional mode; The benefit of JTAG is we don't have to break the circuit physically to perform the test.
  • there are ways (some patented) to make individual pins controllable for fault injection (FPGAs, ASICs, PLDs); taking a device out of functional mode not necessarily needed;
  • Many times, the boards modified for Fault Injection do not represent the real world operating environment for the board
http://www.sjtag.org/minutes/minutes071217.html
- Heiko

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Re: Major Takeway Points

Post by eric.cormack » Mon Jan 24, 2011 2:52 pm

Review of Minutes for Q3-2008

Minutes of Weekly Meeting, 2008-07-07: http://www.sjtag.org/minutes/minutes080707.html
  • No key take-aways
Minutes of Weekly Meeting, 2008-07-16: http://www.sjtag.org/minutes/minutes080716.html
  • Guidelines on how you deal with best practices for items such as gateways and others that lets you leverage the technologies best
  • Need to understand whether we need a language for the application or a language set for transfer of test information between tools and other aspects
  • Use Case - Structural Test: Heiko’s discussion on the synchronization issues with 1149.6 regarding the test across multiple chains (e.g., multi-drop issues or multiple chain synchronization issues)
Minutes of Weekly Meeting, 2008-07-28: http://www.sjtag.org/minutes/minutes080728.html
  • Brad’s BTW2006 Presentation on SJTAG interfaces
  • Scope and Purpose: We need to think of what the deliverables are; IEEE 1149.5 was a system level JTAG standard, and it failed

Minutes of Weekly Meeting, 2008-08-04: http://www.sjtag.org/minutes/minutes080804.html
  • Scope and Purpose statement
  • IEEE1149.5 was overwhelming, just for the implementation there was too much to read and absorb; SJTAG should try to be simpler to implement
  • Addition of "configuration" and "programming" to the list of features we provide as a method of access for?
  • We should include 1149.4 and 1149.6 too "... describing the structure of IEEE 1149.1 connections ..." (1149.4 has two additional test bus signals, AT1 and AT2, for example)
  • Working within the constraint of just the JTAG 4 or 5 compliant signals
  • Software application programming interfaces - API’s
  • Control of individual chains on the board
Minutes of Weekly Meeting, 2008-08-11: http://www.sjtag.org/minutes/minutes080811.html
  • Use models – Extracting Field return data, Upgrading FPGAs in system, Tie into IJTAG…….
  • Limiting ourselves to 4 or 5 wire JTAG we need to have some support of parallel port access to support write pulse or some other signals
Minutes of Weekly Meeting, 2008-08-18: http://www.sjtag.org/minutes/minutes080818.html
  • Description Language(s)
  • May have to partition tests into pieces that can be autonomous and those that are not
  • All designs may be able to afford placing the test data on the UUT, so alternatives need to be considered
Minutes of Weekly Meeting, 2008-08-27: http://www.sjtag.org/minutes/minutes080827.html
  • Introduction to UML
  • Attributes that could be assigned to a board
Minutes of Weekly Meeting, 2008-09-08: http://www.sjtag.org/minutes/minutes080908.html
  • Merits of generic assembly descriptions vs. board/system descriptions
  • Files from CAD Tools – Relating to definition of assembly
  • Carrier Board with additional mezzanine boards on it – Problems integrating this assembly into a higher system assembly. Need to support this level of hierarchical complexity
  • Hot swap of assemblies causing dynamic aspect to the problem
  • Board ID – is this a mandatory requirement?
  • Extracting test data from the System through the JTAG Port
  • Maybe need ECAD people on the team to input their thoughts
  • Need to be able to query what the configuration is
  • HSDL Discussion – Handling mixed voltages
  • Definition of static paths, external paths, and dynamic paths by HSDL
  • STAPL++ in dealing with concurrent operations

Minutes of Weekly Meeting, 2008-09-15: http://www.sjtag.org/minutes/minutes080915.html
  • System Data Elements – Discussion whether there is a need for descriptions that fall outside of the information that we currently have for the tooling vs. information that can be automatically gleaned or mined from the available information to build up what we traditionally do in something like an HSDL
  • Vendor and 3rd Party Tool support
  • We have all had to create isolations in our circuits to be able to handle these kinds of cases in the secondary chains. Do you people feel that SJTAG should have some sort of standardized way in dealing with this isolation so we can be sure we can have some sort of a chain that can operate independently as well as part of an overall topology or is that something outside of our scope
  • CAD information and various other sources is going to be insufficient to be able to support SJTAG level testing
  • Gunnar's STAPL++ (http://files.sjtag.org/Ericsson-Nov2006/STAPL-Ideas.pdf). Brad presents what Gunnar was presenting to the group. Brad’s feedback to Gunnar was captured in: http://files.sjtag.org/Ericsson-Nov2006 ... edback.doc
    Gunnar presents a strong case and demonstrates clearly why an object oriented perspective is necessary to represent entities at the system level. He also presents a strong case for why current vector languages are inadequate.
Last edited by Ian McIntosh on Fri Jan 28, 2011 9:02 am, edited 1 time in total.
Reason: Change to "slide" layout
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Re: Major Takeway Points

Post by Ian McIntosh » Mon Jan 31, 2011 5:35 pm

Example of format discussed today (use the "Quote" button to open up a reply post that includes the source for this example):

Please note: a single indenting space didn't work very well - a single space at the beginning of a line seems to get ignored by the forum software, and Tab takes the cursor outside of the edit box, so I have used two spaces for each indent level.

Code: Select all

2008-01-07
  http://www.sjtag.org/minutes/minutes080107.html
    Structural Test use case
      Constraints on board edge signals are critical for system level test.
        constraints, board edge, system test
"
  "
    "
      Control of clocks: Don't want to be dependant on system clocks, but may be necessary for testing memories.
        clock control, system clock, memory test
"
  "
    "
      Memory tests must take care not to destroy fault or other essential data.
        memory test, fault data, essential data, destroy data
The generic form is:

Code: Select all

Date (or " to carry date from previous entry)
  URL (or " to carry URL from previous entry)
    Context (or " to carry context from previous entry)
      Comment
        key phrase, key phrase, ...
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Re: Major Takeway Points

Post by Ian McIntosh » Mon Feb 07, 2011 10:22 am

My example above converted the first "record" from my block. Now that Brad has confirmed the format, here are some more:

Code: Select all

2008-01-14
  http://www.sjtag.org/minutes/minutes080114.html
    Structural Test use case
      We need a methodology to lower test generation effort while providing a means to protect IP
        test generation, IP, IP protection
"
  "
    "
      JTAG can allow an OEM vendor to provide a detailed test without exposing IP in the way that a functional test might
        OEM, IP, IP exposure

Code: Select all

2008-01-23
  http://www.sjtag.org/minutes/minutes080123.html
    Structural Test results in embedded execution
      Storage space for results may be limited
        storage space, limitation, constraint, test results, embedded
"
  "
    "
      Should results be transmitted in a standard format?
        results, format, embedded
"
  "
    "
      Is a binary or ASCII format preferred?
        binary, ascii, format, embedded
"
  "
    Structural Test use case
      The level of diagnostic detail required may depend on the test context - where performed, what assembly level
        diagnostic, diagnostic detail, context, assembly level
When I was looking at this one, the nested bullets in the original were creating "sub-contexts" which had me asking whether the higher level bullet was part of the context or part of the comment. In the end I decided that it was better to consider them as "specializing the context". Where no lower level bullet existed then the context I used was the wider one that applied to the whole meeting.

Code: Select all

2008-01-28
  http://www.sjtag.org/minutes/minutes080128.html
    POST use case
      POST execution time is often constrained by a customer requirement
        execution time, constraint, limitation, requirement
"
  "
    "
      OEM implementations may compromise system POST time budgets
        OEM, execution time, time budget
"
  "
    "
      Need method to recover after POST - e.g. to reboot and skip POST requires some semi-persistent state variable
        reboot, state variable, persistent, recovery

Code: Select all

2008-02-04
  http://www.sjtag.org/minutes/minutes080204.html
    POST use case
      Test data should be exported from tools using an existing ASCII format: System integrator/User can then convert to most suitable form for their application
        test data, export, ascii, conversion
"
  "
    "
      For embedded cases, a question over whether a diagnostic is required at run time or data stored for off-line analysis
        embedded, diagnostic, analysis, off-line, run time

Code: Select all

2008-02-11
  http://www.sjtag.org/minutes/minutes080211.html
    POST use case
      Types of test run during POST are application dependant - can't make assumptions
        test types, application, dependancy
"
  "
    "
      POST should be autonomous at the FRU level
        autonomy, FRU
"
  "
    "
      POST need not consider board-to-board test
        board test, exclusion

Code: Select all

2008-02-20
  http://www.sjtag.org/minutes/minutes080220.html
    POST use case
      'A use case is orthogonal to a test.'
        use case, test, quotation
"
  "
    "
      'Use cases help break down the types of tests that are appropriate at each state of a product life cycle.'
        test types, life cycle, use case, quotation
"
  "
    "
      POST is generally intrusive
        intrusion, disruption
"
  "
    System states during POST
      On-line or active, Off, Off-line, Standby
        states
"
  "
    POST use case
      Running POST on a hot-swapped FRU will disrupt system operation
        hot swap, FRU, intrusion, disruption

Code: Select all

2008-02-25
  http://www.sjtag.org/minutes/minutes080225.html
    Programming and Updates use case
      Brad listed several relevant papers from BTW02 and BTW03
        papers, BTW
"
  "
    "
      Need to ensure a board does not become unrecoverable if an update goes wrong
        update error, update failure, recovery
"
  "
    "
      Performing updates via network connection can be a major cost saver
        remote update, cost, network connection
"
  "
    "
      BScan may be a recovery option, complementing more efficient FLASH loading methods
        recovery, flash, alternative methods
Ian McIntosh
Testability Lead
Leonardo MW Ltd.

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Ian McIntosh
SJTAG Chair
Posts: 415
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Location: Leonardo, UK
Contact:

Re: Major Takeway Points

Post by Ian McIntosh » Sat Feb 12, 2011 8:57 pm

I've completed re-formatting all my records, and have now pulled them together into a single block:

Code: Select all

2008-01-07
  http://www.sjtag.org/minutes/minutes080107.html
    Structural Test use case
      Constraints on board edge signals are critical for system level test.
        constraints, board edge, system test
"
  "
    "
      Control of clocks: Don't want to be dependant on system clocks, but may be necessary for testing memories.
        clock control, system clock, memory test
"
  "
    "
      Memory tests must take care not to destroy fault or other essential data.
        memory test, fault data, essential data, destroy data
2008-01-14
  http://www.sjtag.org/minutes/minutes080114.html
    Structural Test use case
      We need a methodology to lower test generation effort while providing a means to protect IP
        test generation, IP, IP protection
"
  "
    "
      JTAG can allow an OEM vendor to provide a detailed test without exposing IP in the way that a functional test might
        OEM, IP, IP exposure
2008-01-23
  http://www.sjtag.org/minutes/minutes080123.html
    Structural Test results in embedded execution
      Storage space for results may be limited
        storage space, limitation, constraint, test results, embedded
"
  "
    "
      Should results be transmitted in a standard format?
        results, format, embedded
"
  "
    "
      Is a binary or ASCII format preferred?
        binary, ascii, format, embedded
"
  "
    Structural Test use case
      The level of diagnostic detail required may depend on the test context - where performed, what assembly level
        diagnostic, diagnostic detail, context, assembly level
2008-01-28
  http://www.sjtag.org/minutes/minutes080128.html
    POST use case
      POST execution time is often constrained by a customer requirement
        execution time, constraint, limitation, requirement
"
  "
    "
      OEM implementations may compromise system POST time budgets
        OEM, execution time, time budget
"
  "
    "
      Need method to recover after POST - e.g. to reboot and skip POST requires some semi-persistent state variable
        reboot, state variable, persistent, recovery
2008-02-04
  http://www.sjtag.org/minutes/minutes080204.html
    POST use case
      Test data should be exported from tools using an existing ASCII format: System integrator/User can then convert to most suitable form for their application
        test data, export, ascii, conversion
"
  "
    "
      For embedded cases, a question over whether a diagnostic is required at run time or data stored for off-line analysis
        embedded, diagnostic, analysis, off-line, run time
2008-02-11
  http://www.sjtag.org/minutes/minutes080211.html
    POST use case
      Types of test run during POST are application dependant - can't make assumptions
        test types, application, dependancy
"
  "
    "
      POST should be autonomous at the FRU level
        autonomy, FRU
"
  "
    "
      POST need not consider board-to-board test
        board test, exclusion
2008-02-20
  http://www.sjtag.org/minutes/minutes080220.html
    POST use case
      'A use case is orthogonal to a test.'
        use case, test, quotation
"
  "
    "
      'Use cases help break down the types of tests that are appropriate at each state of a product life cycle.'
        test types, life cycle, use case, quotation
"
  "
    "
      POST is generally intrusive
        intrusion, disruption
"
  "
    System states during POST
      On-line or active, Off, Off-line, Standby
        states
"
  "
    POST use case
      Running POST on a hot-swapped FRU will disrupt system operation
        hot swap, FRU, intrusion, disruption
2008-02-25
  http://www.sjtag.org/minutes/minutes080225.html
    Programming and Updates use case
      Brad listed several relevant papers from BTW02 and BTW03
        papers, BTW
"
  "
    "
      Need to ensure a board does not become unrecoverable if an update goes wrong
        update error, update failure, recovery
"
  "
    "
      Performing updates via network connection can be a major cost saver
        remote update, cost, network connection
"
  "
    "
      BScan may be a recovery option, complementing more efficient FLASH loading methods
        recovery, flash, alternative methods
2008-03-03 
  http://www.sjtag.org/minutes/minutes080303.html
    Programming and Updates use case
      Routine FPGA configuration via JTAG may lead to excessive board startup times
        FPGA configuration, startup time
"
  "
    "
      Depends on application whether it is better to swap a FRU or to update in the field
        FRU swap, FRU change, field update
2008-03-10
  http://www.sjtag.org/minutes/minutes080310.html
    Programming and Update categories
      Predictable - e.g. for customer requirements - update of application software - programmed via mission bus
        requirements, mission bus, application software
"
  "
    "
      Unpredictable - e.g. maintenance, bug fixes, enhancements - update of CPLD or FPGA code - programmed via various methods
        CPLD update, FPGA update, firmware update, maintenance, bug fix, enhancement
"
  "
    Programming and Updates use case
      NAND Flash present different challenges to NOR Flash
        NAND flash, NOR flash
"
  "
    "
      Loading Boot Code via JTAG, then using Mission Bus for all other loading is a common practice
        boot code, mission bus
2008-03-19 
  http://www.sjtag.org/minutes/minutes080319.html
    Motivation for embedding BScan
      Simplified cabling compared to functional testing
        cabling, functional test, simplification, EST
"
  "
    "
      Short test times suits being used during thermal ramps
        test times, thermal, EST
"
  "
    Environmental Stress Testing use case
      Needs some form of external, overall control
        external control, overall control
"
  "
    "
      Large volumes of test data could be produced - Where do you store it?
        test data, storage
"
  "
    "
      Large volumes of test data could be produced - How (and where) do you analyse it?
        test data, analysis
"
  "
    "
      BScan may stress the board more than mission mode operation
        stress, mission mode
2008-03-31 
  http://www.sjtag.org/minutes/minutes080331.html
    Programming and Update value proposition
      TCK speeds are a problem for programming large FPGA/Flash devices
        TCK, FPGA, flash
"
  "
    "
      FPGAs and CPLDs will lose functional mode while device programming is taking place
        FPGA, CPLD, functional mode
"
  "
    "
      STAPL or SVF may be adequate languages for programming
        STAPL, SVF, languages
Last edited by Ian McIntosh on Mon Feb 14, 2011 1:50 pm, edited 1 time in total.
Reason: Added missing comma
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Bradford Van Treuren
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Re: Major Takeway Points

Post by Bradford Van Treuren » Sun Feb 27, 2011 9:49 pm

Here is my posting for Q3 2009 Meeting Minutes

Code: Select all

2009-07-13
  http://www.sjtag.org/minutes/minutes090713.html
    2009 Survey Discussion
      We are targeting the whole spectrum from Test Engineers, Designers, Engineering Management, etc.
        2009 Survey
"
  "
    "
      Sections 1 and 2 are for a "calibration" on the user so we can adjust our interpretation of subsequent answers.
        2009 Survey
2009-07-20
  http://www.sjtag.org/minutes/minutes090720.html
    Root Cause Analysis/Failure Mode Analysis
      Sampling vehicles include temperature sensors and other instruments.
        White Paper,Root Cause,FMA
"
  "
    "
      The Value Proposition here is the shorter turn round time on the solution.
        White Paper,Root Cause,FMA
"
  "
    "
      Trending: changing the mind set on data collecting to see things that you'd otherwise overlook.
        White Paper,Root Cause,FMA
"
  "
    "
      The major consequence will be the need for more storage on the board.
        White Paper,Root Cause,FMA
"
  "
    "
      We have to consider the data format of the FMA data storage.
        White Paper,Root Cause,FMA
"
  "
    "
      Do we make FMA data available during power off?
        White Paper,Root Cause,FMA
2009-07-27
  http://www.sjtag.org/minutes/minutes090727.html
    Power-On Self-Test
      You've already got JTAG tests from your manufacturing operations that you can leverage into the product for a BSCAN enhanced POST.
        POST, White Paper
"
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      POST needs to run in a certain time window.
        POST, White Paper
"
  "
    "
      POST and BIST are not the same thing.  Differences enumerated.
        POST, White Paper
"
  "
    "
      The test infrastructure is already there, perhaps less the controller.
        POST, White Paper.
"
  "
    "
      Some things get tested at power up, others after the firmware has loaded.
        POST, White Paper
"
  "
    "
      Functional test tends to check functions sequentially, while JTAG may test many data paths in parallel, so JTAG will usually give better coverage within the same time constraint.
        POST, White Paper
"
  "
    "
      The test will essentially corrupt the core logic on the board, so you need some form of reset that doesn't then re-run the POST. Some people use an on-demand BIST only followed by a reset; that way they can ignore BSCAN on power up.POST, White Paper
        POST, White Paper
2009-08-03
  http://www.sjtag.org/minutes/minutes090803.html
    Environmental Stress Test
      The difference between embedded and external test. In embedded testing I can use the same Ethernet connection for reporting boundary can results that I would use for functional test.
        EST, White Paper, Embedded Test, External Test
"
  "
    "
      We need to have some way of looping tests.
        EST, White Paper, Embedded Test, External Test
"
  "
    "
      We need to be able to correlate with external events.
        EST, White Paper, Embedded Test, External Test
"
  "
    "
      Loopbacks can be added for testing at EST.
        EST, White Paper, Embedded Test, External Test
"
  "
    "
      Advantage of embedded testing is that it allows parallelism in execution that is difficult to get with external test.
        EST, White Paper, Embedded Test, External Test
2009-08-10
  http://www.sjtag.org/minutes/minutes090810.html
    Device Versioning
      The major points for device versioning are the ability to determine what vendor part is installed and what revision of that part is present.
        Device Versioning, White Paper
"
  "
    "
      USERCODE strategy has to be planned.
        Device Versioning, White Paper, USERCODE
"
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    "
      BScan may be able to access I2C version information.
        Device Versioning, White Paper, I2C
"
  "
    "
      A new USERCODE may need a customized BSDL file.
        Device Versioning, White Paper, USERCODE
2009-08-17
  http://www.sjtag.org/minutes/minutes090817.html
    2009 Survey
      The need for concurrency may eliminate the ability to use SVF or STAPL as the future test languages.
        2009 Survey, Concurrency
"
  "
    "
      Netlists are good examples of managing separate instances without the need for Object-Oriented modeling.
        2009 Survey, Model, Netlist, Object-Oriented
2009-08-24
  http://www.sjtag.org/minutes/minutes090824.html
    Device Versioning
      Versioning extends to board and system configuration.
        Device Versioning
2009-08-31
  http://www.sjtag.org/minutes/minutes090831.html
    Device Versioning
      GNAT example for example of 1149.1 instrumentation.
        Device Versioning,Instruments,GNAT
2009-09-14
  http://www.sjtag.org/minutes/minutes090914.html
    Device Versioning
      Group had difficulty defining Configurtion so the discussion was taken to the forums.
        Configuration, White Paper, Device Versioning
"
  "
    "
      Forum discussions on variations of structure in regards to configuration.
        Configuration, White Paper, Device Versioning, Structure
"
  "
    "
      Physical inspection of devices may not always be possible because markings are obscured.
        Configuration, White Paper, Device Versioning, Inspection
"
  "
    "
      Inventory PROMs may be used to preserve configuration information.
        Configuration, White Papter, Device Versioning
2009-09-21
  http://www.sjtag.org/minutes/minutes090921.html
    Device Versioning
      There is a need to support multiple IDCODEs from multiple vendors for compatible devices for a single instance.
        Configuration, White Paper, Device Versioning, IDCODE
"
  "
    "
      BSDL register description for USERCODE seems to be insufficient to support all possible combinations of configurations.
        Configuration, White Paper, Device Versioning, USERCODE, BSDL
"
  "
    "
      Tooling requirements for device configuration.
        Configuration, White Paper, Device Versioning, USERCODE, BSDL
"
  "
    "
      Device configuration also includes firmware versions, registered parameters, USERCODE, IDCODE, and tuning parameters all of which affects BSDL stability.
        Configuration, White Paper, Device Versioning, USERCODE, BSDL, IDCODE, firmware
"
  "
    "
      BSDL needs to support sets of codes instead of single codes.
        Configuration, White Paper, Device Versioning, USERCODE, BSDL, IDCODE
2009-09-28
  http://www.sjtag.org/minutes/minutes090928.html
    Device Versioning
      IDCODE and USERCODE sampling is non-intrusive operations, so a board can stay on-line during interrogation.
        Configuration, White Paper, Device Versioning, USERCODE, IDCODE
"
  "
    "
      IDCODES and chain topology are not enough to determine a board's version or model.
        Configuration, White Paper, Device Versioning, IDCODE
Bradford Van Treuren
Distinguished Member of Technical Staff
NOKIA MN

User avatar
Heiko Ehrenberg
SJTAG Vice Chair
Posts: 45
Joined: Wed Nov 21, 2007 3:15 pm
Location: GOEPEL Electronics - Austin, TX
Contact:

Re: Major Takeway Points

Post by Heiko Ehrenberg » Mon Feb 28, 2011 10:03 pm

Here is an attempt to reformat my meeting summaries for Q4 2007:

Code: Select all

2007-10-05
  http://www.sjtag.org/minutes/minutes071005.html
    System Under Test
      Need to support 3 views for JTAG on each board: Edge access from the backplane, local embedded JTAG controller, and External Tester interface
        backplane, controller, ATCA, microTCA
"
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    "
      at least in ATCA, interoperability between vendor blades [boards] is going to be key
        ATCA, interoperability
"
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    "
      a system needs to support a uniform protocol at the backplane so boards may be purchased from multiple vendors and conform to the same testing interface for the system to be able to work
        protocol, interoperability
"
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    "
      key considerations for SJTAG include: signal integrity, performance, protocol isolation / multi-vendor interoperability, signal voltage levels (microTCA: 3.3V; Patrick: we may need lower voltages, I/O level flexibility), and real estate available for JSM implementation and signal routing;
        Signal integrity, protocol, interoperability, voltage level, JSM
2007-10-19
  http://www.sjtag.org/minutes/minutes071019.html
    SJTAG requirements
      need to emphasize that carrier blades are really subsystem, requiring their local JTAG infrastructure to be immune to changes in the AMC blade configuration
        key phrase, key phrase, ...
"
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    "
      need to be able to hot-swap blades that are "off-line", needs to be managed by system software, prohibit blades to be removed (put in hot-swap mode) that are currently being tested; 
        key phrase, key phrase, ...
2007-11-12
  http://www.sjtag.org/minutes/minutes071112.html
    Retaining fault diagnostics in the system
      Some systems will test at PCB level with one vendor and at system level diagnostic by another. Info must be transferable between vendors.
        key phrase, key phrase, ...
2007-11-19
  http://www.sjtag.org/minutes/minutes071119.html
    Retaining fault diagnostics in the system
      we need to show the cost advantages for using system level JTAG;
        key phrase, key phrase, ...
2007-11-26
  http://www.sjtag.org/minutes/minutes071126.html
    ATCA HUB board
      When implementing a 4-pin JTAG interface hosted from ATCA HUB boards which must also be tested by external tester, we need a connector (interface) for the external tester;
        key phrase, key phrase, ...
"
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    "
      interface must be on HUB board to facilitate connection and arbitration to the system; real problem is the arbitration of which ATCA HUB is going to be master;
        key phrase
"
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      Embedded boundary-scan controller must not be active on backplane by default, to allow external tester to drive the chain (external tester could then be the primary access point by default);
        key phrase
2007-12-17
  http://www.sjtag.org/minutes/minutes071217.html
    SJTAG Value Proposition - Fault Injection
      physical modifications (wires, extender cards, ...) may be needed to insert faults, but this may not allow simulation of real faults, also, it changes the environment (systems cannot be sealed, temperature changes, etc.); 
        key phrase
"
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    "
      extender cards and similar physical modifications also degrade performance of the system by changing the characteristics of the nets;
        key phrase
"
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    "
      problem with JTAG is that putting a device into EXTEST takes all of its pins out of functional mode; The benefit of JTAG is we don't have to break the circuit physically to perform the test;
        key phrase
"
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      there are ways (some patented) to make individual pins controllable for fault injection (FPGAs, ASICs, PLDs); taking a device out of functional mode not necessarily needed; 
        key phrase
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      Many times, the boards modified for Fault Injection do not represent the real world operating environment for the board.
        key phrase
For the following meetings I wasn't able to identify key takeaway points:

2007-10-12
~~~~~~~~~~
- more details on ATCA

2007-10-29
~~~~~~~~~~
- no key takeaway

2007-11-05
~~~~~~~~~~
- discussion of the role SJTAG should play in a system

2007-12-03
~~~~~~~~~~
- discussion on "What are we trying to achieve?"
- started discussion on use cases;

2007-12-10
~~~~~~~~~~
- discussion of operating procedures for group;
- decision to use forum for SJTAG use case discussions
- Heiko

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